In order to achieve high circuit performance and density, MOSFET (metal-oxide-semiconductor field effect transistor) devices in silicon integrated circuit technology are scaled down to submicrometer range. In scaling down MOSFETs, the reduction of device dimensions is not accompanied by a corresponding reduction in power requirements. As a result, NMOS (n-channel MOS) devices are susceptible to channel hot-electron (CHE) instability. See Chenming Hu et al., "Hot-Electron-Induced MOSFET Degradation - Model, Monitor and Improvement," IEEE Transactions on Electron Devices, Vol. ED-32, No. 2 (Feb. 1985), pp. 375-385. The instability is caused by the very high electric field near the drain junction resulting from the short channel length and high supply voltage.
Another difficulty caused by scaling down is the increase in the resistance of the diffused layers. This results in increased signal delays along diffused interconnects and degrades circuit performance due to the large source/drain series resistance.
To alleviate the high electric field at the reduced MOSFET channel length, lightly doped drain (LDD) devices have been proposed. See K. Saito et al, "A New Short Channel MOSFET with Lightly Doped Drain," Denshi Tsushin Rengo Taikai (in Japanese) (April 1978), p. 220. In the LDD structure, narrow, self-aligned, n.sup.- regions are introduced between the channel and the N.sup.+ source/drain regions. The N.sup.- region spreads the high electric field out near the drain junction, allowing the device to be operated at a higher supply voltage with fewer hot-electron problems.
Several processes for fabricating lightly-doped drain field effect transistor (LDDFET) have been proposed. Spacer and overhang techniques are most commonly adopted. The spacer technique involves a reactive-ion etching (RIE) step after silicon dioxide is chemical vapor deposited to form side wall oxide spacers. Oxide spacers are used to mask the heavy and deep implant of the N.sup.+ drain/source regions after the formation of the shallow n.sup.- drain/source regions. See FIG. 2, p. 590, of Paul J. Tsang et al., "Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology," IEEE Transactions on Electron Devices, Vol. ED-29, No. 4 (April 1982). The overhang technique involves a polysilicon over-etching step after SiO.sub.2 /Si.sub.3 N.sub.4 /poly-Si/SiO.sub.2 gate stack is patterned to form SiO.sub.2 /Si.sub.3 N.sub.4 overhangs. SiO.sub.2 /Si.sub.3 N.sub.4 overhangs are used to mask the heavy and deep implant of the n.sup.+ drain/source regions followed by the formation of the shallow n.sup.- drain/source regions. See FIG. 2, p. 1360, of Seiki Ogura et al., "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor," IEEE Transactions on Electron Devices, Vol, ED-27, No. 8 (Aug. 1980).
Unfortunately, in the spacer technology, additional oxide deposition and oxide etch-back processes are needed. In the overhang technology, additional Si.sub.3 N.sub.4 /SiO.sub.2 deposition and polysilicon over-etching processes are required. In addition, two ion implantation steps are necessary and, therefore, these processes are far too complicated for commercial application.
Two alternative structures, buried LDD and graded/buried LDD structures adopting sidewall oxide spacer technology, have also been demonstrated. See Ching-Yeu Wei et al., "Buried and Graded/Buried LDD Structures for Improved Hot-Electron Reliability," IEEE Electron Device Letters, Vol. EDL-7, No. 6 (June 1986), pp. 380-382.
Still another method described is the so-called self-defined polysilicon sidewall (SEPOS) technique which uses SiO.sub.2 at the vertical sides of the polysilicon to define the oxide-framed polysilicon sidewall. See FIG. 1, p. 2463, of M. Saitoh, "Degradation Mechanism of Lightly Doped Drain (LDD) n-channel MOSFET's Studied by Ultraviolet Light Irradiation," J. Electrochem. Soc.: Solid-State Science and Technology, Vol. 132, No. 10 (Oct. 1985), pp. 2463-2466.
Also proposed has been the self-aligned polysilicon source/drain (SAPSD) technique which uses an N.sup.+ polysilicon source/drain layer to allow the dopants to diffuse into the substrate to form the n.sup.- region. See FIG. 1, p. 314, of Tiao-Yuan Huang et al., "A MOS Transistor with Self-Aligned Polysilicon Source-Drain," IEEE Electron Device Letters, Vol. EDL-7, No. 5 (May 1986), pp. 314-316. In general, all the techniques mentioned above are too difficult and complex processes.
In addition, a new LDD structure for NMOS FET has been demonstrated. It may be made using a single ion implantation step to form n.sup.- regions due to the sloped sidewall of the structure. See FIG. 1, p. 28, of "A New Structure LDD for NMOSFET," Japan Semiconductor News, Vol. 3, No. 3 (June 1984), pp. 27-28. Unfortunately, the gate of the FET is much higher than source/drain regions.
Recently, the inverse-T LDD (ITLDD) transistor has been proposed (T. Y. Huang et al., "A Novel Submicron LDD Transistor with Inverse-T Gate Structure," IEDM 86 (International Electron and Device Meeting 1986), Sec. 31.7, pp. 742-745). The main feature of the ITLDD transistor is the self-aligned n.sup.- LDD and N.sup.+ source/drain implants in the inside and outside edges, respectively, of the inverse-T gate structure. In ITLDD, the spacer-induced degradation in a conventional LDD transistor is eliminated as a result of the self-aligned n.sup.+ -to-gate feature. In this scheme, wafers are processes using the conventional process up to the formation of the polysilicon gate pattern. Instead of etching away the entire polysilicon layer as is conventional in the preparation of LDD transistors, the polysilicon etch is deliberately stopped so as to leave a thin polysilicon layer of about 50-100 nm. A phosphorus n.sup.- dose with proper energy is then implanted to form the n.sup.- LDD region and a CVD oxide layer is deposited and anisotropically etched to form an oxide sidewalls-spacer. The oxide sidewall-spacer, as in the case of conventional LDD transistor processing, serves as the mask to offset n.sup.+ source/drain implant, allowing optimization of the length of n.sup.- region. A plasma polysilicon etch or a light reoxidation can then be used to strip off (or oxidize) the remaining thin polysilicon. This completes the definition of the inverse-T gate structure, resulting in an oxide sidewall-spacer abutting the ledge of the IT gate. Since the thin polysilicon layer which forms part of the IT gate is protected on the top by the thick oxide sidewall-spacer, it is preserved during reoxidation. A shallow arsenic n.sup.+ implant is then performed to form the source/drain region. The n.sup.+ source/drain implant is self-aligned to the polysilicon gate and therefore the n.sup.+ -to-gate offset is eliminated. See FIG. 2, p. 743, of Huang et al., supra.
Another technology to overcome the series resistance problem, known as self-aligned salicide (salicide) technology, has been proposed. This approach reduces device series resistance and enhances interconnects. See C. M. Osburn et al., "High Conductivity Diffusions and Gate Regions using Self-Aligned Silicide Technology," Electrochemical Society Proceedings, First International Symposium VLSI Science and Technology, Vol. 82-7 (1982), pp. 213-223. In salicide technology, a gate sidewall oxide is formed which protects the gate sidewall from shorting to the source/drain regions after salicidation. The gate sidewall oxide if formed either by depositing and anisotropically etching a CVD oxide layer or by selective oxidation of sidewalls of the gate on which there is a layer of silicon nitride. See FIG. 1 and FIG. 2, p. 222, of C. M. Osburn et al., "High Conductivity Diffusions and Gate Regions Using Self-Aligned Silicide Technology," Electrochemical Society Proceedings, First International Symposium VLSI Science and Technology, Vol. 82-7, 1982.
Combining LDD with salicide technologies has been reported. See FIG. 6, p. 347, of Fang-Shi J. Lai et al., "Design and Characteristics of a Lightly Doped Drain (LDD) Device Fabricated with Self-Aligned Titanium Disilicide," IEEE Transactions on Electron Devices, Vol. ED-33, No. 3 (March 1986), pp. 345-353. However, the fabrication of the LDDFET requires additional depositing and etching of chemical vapor deposited films and two ion implantation steps. Accordingly, the process is far too complicated.